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TBB1016
Twin Built in Biasing Circuit MOS FET IC VHF/VHF RF Amplifier
REJ03G1327-0200 Rev.2.00 Aug 22, 2006
Features
* * * * * * Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Very useful for total tuner cost reduction. Suitable for World Standard Tuner RF amplifier. High gain; PG = 32 dB at 200 MHz Low noise; NF = 1.0 dB at 200 MHz Power supply voltage: 5 V
Outline
RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6)
6 5 4
2 1
3
1. Drain(1) 2. Source 3. Drain(2) 4. Gate-1(2) 5. Gate-2 6. Gate-1(1)
Notes:
1. Marking is "RM". 2. TBB1016 is indivisual type number of RENESAS TBBFET.
Absolute Maximum Ratings
(Ta = 25C)
Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Symbol VDS VG1S VG2S Ratings 6 +6 -0 +6 -0 30 250 150 -55 to +150 Unit V V V mA mW
C C
Drain current ID Channel power dissipation PchNote3 Channel temperature Tch Storage temperature Tstg Note: 3. Value on the glass epoxy board (50 mm x 40 mm x 1 mm)
Rev.2.00
Aug 22, 2006
page 1 of 9
TBB1016
Electrical Characteristics
* The below specification are applicable for FET1 and FET2 unit (Ta = 25C)
Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss PG NF Min 6 +6 +6 -- -- 0.5 0.4 11 30 1.8 0.9 27 -- Typ -- -- -- -- -- 0.8 0.7 15 35 2.2 1.3 32 1.0 Max -- -- -- +100 +100 1.1 1.0 19 42 2.6 1.7 37 1.7 Unit V V V nA nA V V mA mS pF pF dB dB Test Conditions ID = 200 A, VG1S = VG2S = 0 IG1 = +10 A, VG2S = VDS = 0 IG2 = +10 A, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 A VDS = 5 V, VG1S = 5 V, ID = 100 A VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 k VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 120 k VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 120 k VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k, f = 200 MHz
Rev.2.00
Aug 22, 2006
page 2 of 9
TBB1016
DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, NF, PG)
* Measurement of FET1
VG2
Gate 2 RG Gate 1(1) Open
VG1
ID VD
A Drain (1) Source Open
* Measurement of FET2
VG2
Gate 2 Open Gate1(2) RG
VG1
A Open Source Drain (2)
ID VD
Rev.2.00
Aug 22, 2006
page 3 of 9
TBB1016
200 MHz Power Gain, Noise Figure Test Circuit
VT 1000 p VG2 1000 p VT 1000 p
47 k Input (50 ) 1000 p 36 p L1
1000 p
47 k L2 1000 p
47 k
Output (50 )
10 p max 1000 p HVU202A R1 1000 p VG1 1000 p VD Unit : Resistance () Capacitance (F) RFC HVU202A
R1 : 120 k L1 : 1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns L2 : 1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns RFC : 1 mm Enameled Copper Wire, Inside dia 5 mm, 2 Turns
Rev.2.00
Aug 22, 2006
page 4 of 9
TBB1016
Main Characteristics
Maximum Channel Power Dissipation Curve
Channel Power Dissipation Pch* (mW)
400
25
Typical Output Characteristics
VG2S = 4 V VG1 = VDS
Drain Current ID (mA)
300
20
15
200
10
100
5
0
50
100
150
200
0
1
2
3
4
12
k 0 15 k 0 18 k 0 22
R G= 10 82 0 0k k k
5
Ambient Temperature Ta (C)
* Value on the glass epoxy board (50 mm x 40 mm x 1 mm)
Drain to Source Voltage VDS (V)
Drain Current vs. Gate1 Voltage
25
Forward Transfer Admittance vs. Gate1 Voltage
Forward Transfer Admittance |yfs| (mS)
50 VDS = 5 V RG = 120 k 40 f = 1 kHz
Drain Current ID (mA)
20
VDS = 5 V RG = 120 k
4V
4V 3V
15
3V 2V
30
10
20
2V
5
VG2S = 1 V
0 1 2 3 4 5
10
VG2S = 1 V
0 1 2 3 4 5
Gate1 Voltage VG1 (V)
Gate1 Voltage VG1 (V) Input Capacitance vs. Gate2 to Source Voltage
5
Drain Current vs. Gate Resistance
30
Drain Current ID (mA)
25 20 15 10 5 0 10 VDS = VG1 = 5 V VG2S = 4 V 20 50 100 200 500 1000
Input Capacitance Ciss (pF)
4
3
2
1
VDS = VG1 = 5 V RG = 120 k f = 1 MHz 0 1 2 3 4
0
Gate Resistance RG (k)
Gate2 to Source Voltage VG2S (V)
Rev.2.00
Aug 22, 2006
page 5 of 9
TBB1016
Power Gain vs. Gate Resistance
35 3
Noise Figure vs. Gate Resistance
VDS = VG1 = 5 V VG2S = 4 V f = 200 MHz 2
25
15 VDS = VG1 = 5 V VG2S = 4 V f = 200 MHz 5 10 20 50 100 200 500 1000
Noise Figure NF (dB)
Power Gain PG (dB)
1
0 10
20
50
100
200
500 1000
Gate Resistance RG (k)
Gate Resistance RG (k)
Power Gain vs. Gate2 to Source Voltage
40 5
Noise Figure vs. Gate2 to Source Voltage
VDS = VG1 = 5 V RG = 120 k f = 200 MHz
30
Noise Figure NF (dB)
4
Power Gain PG (dB)
4
3
20
2
10
VDS = VG1 = 5 V RG = 120 k f = 200 MHz 1 2 3
1
0
0 1 2 3 4
Gate2 to Source Voltage VG2S (V)
Gate2 to Source Voltage VG2S (V)
Gain Reduction vs. Gate2 to Source Voltage
50
Gain Reduction GR (dB)
40
VDS = VG1 = 5 V RG = 120 k f = 200 MHz
30
20
10
0 0 1
2
3
4
Gate2 to Source Voltage VG2S (V)
Rev.2.00
Aug 22, 2006
page 6 of 9
TBB1016
S11 Parameter vs. Frequency
.8 .6 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 -10 -.2 -5 -4 -3 -.4 -2 -.6 -.8 -1 -1.5 -120 -90 -60 180 0 150 30 1 1.5 2 120
S21 Parameter vs. Frequency
90
Scale: 5 / div.
60
-150
-30
Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k 0.05 to 1.0 GHz (0.05 GHz step)
Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k 0.05 to 1.0 GHz (0.05 GHz step)
S12 Parameter vs. Frequency
90 120
S22 Parameter vs. Frequency
.8 .6 .4 3 1 1.5 2 30 .2
Scale: 0.05 / div.
60
150
4 5 10
180
0
0
.2
.4
.6 .8 1
1.5 2
3 45 -10
-.2 -150 -30 -.4 -2 -120 -90 -60 -.6 -.8 -1 -1.5
-5 -4 -3
Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k 0.05 to 1.0 GHz (0.05 GHz step)
Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k 0.05 to 1.0 GHz (0.05 GHz step)
Rev.2.00
Aug 22, 2006
page 7 of 9
TBB1016
S parameter
(VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 k, Zo = 50 )
Freq. (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 S11 Mag 0.994 0.992 0.987 0.985 0.975 0.967 0.960 0.952 0.940 0.934 0.914 0.904 0.892 0.881 0.870 0.855 0.839 0.827 0.809 0.796 Deg -3.7 -7.6 -11.1 -14.8 -18.6 -21.9 -25.4 -28.9 -32.2 -35.7 -38.8 -42.1 -45.4 -48.8 -51.5 -54.4 -57.5 -60.3 -62.8 -65.7 Mag 3.73 3.72 3.72 3.70 3.71 3.69 3.68 3.65 3.64 3.62 3.58 3.58 3.55 3.52 3.51 3.49 3.47 3.48 3.43 3.43 S21 Deg 175.3 170.7 166.1 161.7 157.0 152.9 148.1 143.8 138.9 134.7 130.0 125.9 121.4 116.9 112.5 107.9 103.7 99.3 95.0 90.3 Mag 0.002 0.003 0.004 0.004 0.005 0.005 0.004 0.006 0.006 0.006 0.006 0.006 0.005 0.004 0.004 0.004 0.004 0.004 0.005 0.007 S12 Deg 88.4 107.7 54.7 62.4 81.1 83.3 65.3 68.8 77.6 69.3 77.0 45.7 66.8 52.5 93.5 92.7 121.0 140.2 167.7 171.4 Mag 0.992 0.996 0.992 0.990 0.990 0.984 0.982 0.982 0.972 0.971 0.965 0.959 0.955 0.948 0.949 0.941 0.936 0.929 0.921 0.921 S22 Deg -2.4 -5.1 -7.2 -9.6 -12.0 -14.6 -17.1 -19.4 -21.9 -24.6 -26.9 -29.9 -32.5 -35.6 -38.3 -41.4 -44.4 -47.7 -50.9 -54.5
Rev.2.00
Aug 22, 2006
page 8 of 9
TBB1016
Package Dimensions
Package Name CMPAK-6 JEITA Package Code SC-88 RENESAS Code PTSP0006JA-A Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g
D e
A Q c
E
HE LP L
A xM
A SA b
L1
A3 e
Reference Symbol
Dimension in Millimeters
A2
A
yS b b1 c c1
A1 S e1
l1
b2 A-A Section Pattern of terminal position areas
A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x y b2 e1 l1 Q
Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2
Nom 0.9 0.25 0.22 0.2 0.13 0.11 2.0 1.25 0.65 2.1
Max 1.1 0.1 1.0 0.3 0.15 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 0.9
1.5 0.25
Ordering Information
Part Name TBB1016RMTL-E Quantity 3000 pcs Shipping Container 178mm reel, 8mm emboss taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.
Rev.2.00
Aug 22, 2006
page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0

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